1. Technical Field
The present disclosure relates to a digital/analog converting driver and, more particularly, to a digital/analog converting driver including a resistor string converter and a capacitor converter.
2. Discussion of the Related Art
Recently, as the size of a display panel such as used in a television is being increased, the number of digital/analog converters necessary for driving the panel in a source driver IC is also increasing.
Accordingly, as the semiconductor chip area of the digital/analog converter increases, the chip area of the source driver in the display device also increases. This problem seems to be more serious in a 10-bit system for displaying high definition television signals.
FIG. 1 schematically illustrates a conventional resistor string digital/analog converter.
Referring to FIG. 1, the conventional resistor string digital/analog converter 10, hereinafter, referred to as a “resistor string converter, includes a resistor string 12 and a decoder 14.
When the bit number of the digital data DTA input to the resistor string converter 10 is n, the resistor string 12 includes 2n−1 resistors R1, R2, . . . , and R2n−1 which are connected in series. A maximum voltage Vmax and a minimum voltage Vmin are applied across the resistor string 12.
The respective voltages Vi1, Vi2, . . . , and Vik across the resistors R1, R2, . . . , and R2n−1 have voltages between the maximum voltage Vmax and the minimum voltage Vmin.
The decoder 14 receives the digital data DTA and selects and outputs a voltage corresponding to the received digital data DTA from the voltages Vi1, Vi2, . . . , and Vik of the resistor string 12.
The voltages Vo1, Vo2, . . . , and Vok selected by the decoder 14 are supplied to an external device through respective buffers in a buffer unit 20 as analog voltages.
The conventional resistor string converter of FIG. 1 can perform a stable digital/analog converting function. Whenever the bit number of the digital data increases one by one, however, the chip area of the conventional resistor string converter increases by two times.
For example, if the size of a decoder in a 6-bit system is 100, the size of a decoder in an 8-bit system is 400 (100×22). Similarly, the size of a decoder in a 10-bit system is 1600(100×24) and the size of a decoder in a 12-bit system is 3200(100×26).
Accordingly, the resistor string converter is not suitable for a high level of integration and cannot be used in the 10-bit system, for example.
In order to address this problem, a capacitor digital/analog converter, hereinafter, referred to as capacitor converter has been proposed.
FIG. 2 is a circuit diagram illustrating a conventional capacitor converter.
Referring to FIG. 2, the conventional capacitor converter 30 includes an inputting unit 32 and a converting unit 34.
The inputting unit 32 includes switches Sd1 and Sd2, and selects reference voltage Va or Vb according to the logical level of a bit in the input digital data DTA and outputs the selected reference voltage to the converting unit 34.
The converting unit 34 includes a first capacitor C1, a second capacitor C2, and switches Sc1, Sc2, and Sc3. The converting unit 34 repeatedly performs charging and charge distributing operations and outputs an analog voltage V0 having a level corresponding to the input digital data DTA.
The capacitor converter 30 operates as follows.
First, an initial switch Sc3 discharges the first capacitor C1 and the second capacitor C2 prior to conversion. The inputting unit 32 outputs either one of the reference voltages Va or Vb to the converting unit 34 according to the logical level of a first bit of the input digital data DTA.
A charging switch Sc1 is closed so that the first capacitor C1 is charged by the reference voltage Va or Vb output from the inputting unit 32.
Next, the charging switch Sc1 is opened and a distribution switch Sc2 is closed such that the charges stored in the first capacitor C1 are distributed to the second capacitor C2. At this time, the first capacitor C1 and the second capacitor C2 have the same voltage Va/2 or Vb/2.
Next, the first capacitor C1 is charged by any one of the reference voltages Va and Vb according to the logical level of a second bit of the digital data DTA and the charges are then distributed to the first capacitor C1 and the second capacitor C2.
When digital data having n bits is used, the above processes are performed n times and, thus, an analog voltage Vo having a level corresponding to the input digital data DTA is generated.
Since the conventional capacitor converter includes only a predetermined number of switches and two capacitors regardless of bit number of the digital data, the area thereof is reduced relative to that of the resistor string converter.
When the 10-bit system is composed of the capacitor converter, the area thereof is the same as that of the 6-bit system composed of the resistor string converter.
Since the capacitor converter generates a desired analog voltage through charge distribution from a least significant bit to a most significant bit in the digital data as described above, however, an error may be generated when decoding the most significant bit.
More specifically, if only the logical level of the most significant bit is different from that of the other bits, such as “01111111” or “10000000”, the error probability will be increased.
Referring back to FIG. 2, suppose that the reference voltages Va and Vb of the capacitor converter 30 are 5 V and 0 V, respectively, and the digital data DTA is “01111111” (the least significant bit is the first bit to be input).
The charging and distributing operations of the first capacitor C1 and the second capacitor C2 are performed by the logical level “1” of the first bit of the digital data DTA (the least significant bit is the first bit to be input) and, thus, the analog voltage Vo becomes 2.5 V.
Next, when the voltage of 5 V is input according to the logical level “1” of a second bit of “101111111”, the voltage division between the first capacitor C1 having 5 V and the second capacitor C2 having 2.5 V are performed and, thus, the analog voltage Vo becomes 3.75 V.
The above process is repeatedly performed. Thereafter, when decoding the logical level “1” of an n−1th bit, a voltage close to the reference voltage (5 V) is output. In other words, after an n−1th converting process, the second capacitor C2 is charged by a voltage close to the maximum Va, which is 5 V.
When the first capacitor C1 is charged by the reference voltage (0 V) according to the logical level “0” of an nth bit and the voltage division between the first capacitor C1 and the second capacitor C2 is performed, however, a switching error is typically generated due to a large voltage difference between the capacitors C1 and C2.
Since the switching error is generated when converting the most significant bit for generating a final analog voltage corresponding to the digital data, the error probability is large. As the bit number of the digital data increases, the voltage difference between the capacitors C1 and C2 increases. Thus, the error probability increases even further.
According to the conventional capacitor converter as the bit number of the digital data increases, the error generation frequency also increases. Thus, it is impossible to ensure stability of a multi-bit system using the conventional capacitor converter.